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You are on page 1of 150

)

M. B. Patil

mbpatil@ee.iitb.ac.in

www.ee.iitb.ac.in/~sequel

**Department of Electrical Engineering
**

Indian Institute of Technology Bombay

**M. B. Patil, IIT Bombay
**

JK flip-flop: asynchronous inputs

Sd Rd CLK J K Qn+1

Rd 0 1 X X X 0

1 0 X X X 1

J Q

1 1 X X X invalid

CLK

0 0 0 0 Qn

K Q

0 0 0 1 0 normal

Sd operation

0 0 1 0 1

0 0 1 1 Qn

**M. B. Patil, IIT Bombay
**

JK flip-flop: asynchronous inputs

Sd Rd CLK J K Qn+1

Rd 0 1 X X X 0

1 0 X X X 1

J Q

1 1 X X X invalid

CLK

0 0 0 0 Qn

K Q

0 0 0 1 0 normal

Sd operation

0 0 1 0 1

0 0 1 1 Qn

*** Clocked flip-flops are also provided with asynchronous or direct Set and Reset
**

inputs, Sd and Rd , (also called Preset and Clear, respectively) which override all

other inputs (J, K, CLK).

**M. B. Patil, IIT Bombay
**

JK flip-flop: asynchronous inputs

Sd Rd CLK J K Qn+1

Rd 0 1 X X X 0

1 0 X X X 1

J Q

1 1 X X X invalid

CLK

0 0 0 0 Qn

K Q

0 0 0 1 0 normal

Sd operation

0 0 1 0 1

0 0 1 1 Qn

*** Clocked flip-flops are also provided with asynchronous or direct Set and Reset
**

inputs, Sd and Rd , (also called Preset and Clear, respectively) which override all

other inputs (J, K, CLK).

* The Sd and Rd inputs may be active low; in that case, they are denoted by

Sd and Rd .

**M. B. Patil, IIT Bombay
**

JK flip-flop: asynchronous inputs

Sd Rd CLK J K Qn+1

1 0 X X X 1

J Q

1 1 X X X invalid

CLK

0 0 0 0 Qn

K Q

0 0 0 1 0 normal

Sd operation

0 0 1 0 1

0 0 1 1 Qn

*** Clocked flip-flops are also provided with asynchronous or direct Set and Reset
**

inputs, Sd and Rd , (also called Preset and Clear, respectively) which override all

other inputs (J, K, CLK).

* The Sd and Rd inputs may be active low; in that case, they are denoted by

Sd and Rd .

* The asynchronous inputs are convenient for “starting up” a circuit in a known

state.

**M. B. Patil, IIT Bombay
**

D flip-flop

CLK

D Q D Q t

CLK D Qn+1 J

D

CLK 0 0 CLK

t

Q 1 1 K Q Q

**positive edge−triggered D flip−flop t
**

t1 t2 t3 t4 t5

CLK

D Q D Q t

CLK D Qn+1 J

D

CLK 0 0 CLK

t

Q 1 1 K Q Q

**negative edge−triggered D flip−flop t
**

t1 t2 t3 t4 t5

**M. B. Patil, IIT Bombay
**

D flip-flop

CLK

D Q D Q t

CLK D Qn+1 J

D

CLK 0 0 CLK

t

Q 1 1 K Q Q

**positive edge−triggered D flip−flop t
**

t1 t2 t3 t4 t5

CLK

D Q D Q t

CLK D Qn+1 J

D

CLK 0 0 CLK

t

Q 1 1 K Q Q

**negative edge−triggered D flip−flop t
**

t1 t2 t3 t4 t5

* The D flip-flop can be used to delay the Data (D) signal by one clock period.

**M. B. Patil, IIT Bombay
**

D flip-flop

CLK

D Q D Q t

CLK D Qn+1 J

D

CLK 0 0 CLK

t

Q 1 1 K Q Q

**positive edge−triggered D flip−flop t
**

t1 t2 t3 t4 t5

CLK

D Q D Q t

CLK D Qn+1 J

D

CLK 0 0 CLK

t

Q 1 1 K Q Q

**negative edge−triggered D flip−flop t
**

t1 t2 t3 t4 t5

*** The D flip-flop can be used to delay the Data (D) signal by one clock period.
**

* With J = D, K = D, we have either J = 0, K = 1 or J = 1, K = 0; the next Q is 0 in the first

case, 1 in the second case.

**M. B. Patil, IIT Bombay
**

D flip-flop

CLK

D Q D Q t

CLK D Qn+1 J

D

CLK 0 0 CLK

t

Q 1 1 K Q Q

**positive edge−triggered D flip−flop t
**

t1 t2 t3 t4 t5

CLK

D Q D Q t

CLK D Qn+1 J

D

CLK 0 0 CLK

t

Q 1 1 K Q Q

**negative edge−triggered D flip−flop t
**

t1 t2 t3 t4 t5

*** The D flip-flop can be used to delay the Data (D) signal by one clock period.
**

* With J = D, K = D, we have either J = 0, K = 1 or J = 1, K = 0; the next Q is 0 in the first

case, 1 in the second case.

* Instead of a JK flip-flop, an RS flip-flop can also be used to make a D flip-flop, with

S = D, R = D.

**M. B. Patil, IIT Bombay
**

Shift register

Let Q1 = Q2 = Q3 = Q4 = 0 initially.

Q1 Q2 Q3

D D Q D Q D Q D Q Q4

Q Q Q Q

CLK

Shift register

Let Q1 = Q2 = Q3 = Q4 = 0 initially.

Q1 Q2 Q3

D D Q D Q D Q D Q Q4

Q Q Q Q

CLK

CLK

D

Q1

Q2

Q3

Q4

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

time (msec)

Shift register

Let Q1 = Q2 = Q3 = Q4 = 0 initially.

Q1 Q2 Q3

D D Q D Q D Q D Q Q4

Q Q Q Q

CLK

CLK

D

Q1

Q2

Q3

Q4

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

time (msec)

Shift register

Let Q1 = Q2 = Q3 = Q4 = 0 initially.

Q1 Q2 Q3

D D Q D Q D Q D Q Q4

Q Q Q Q

CLK

CLK

D

Q1

Q2

Q3

Q4

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

time (msec)

Shift register

Let Q1 = Q2 = Q3 = Q4 = 0 initially.

Q1 Q2 Q3

D D Q D Q D Q D Q Q4

Q Q Q Q

CLK

CLK

D

Q1

Q2

Q3

Q4

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

time (msec)

Shift register

Let Q1 = Q2 = Q3 = Q4 = 0 initially.

Q1 Q2 Q3

D D Q D Q D Q D Q Q4

Q Q Q Q

CLK

CLK

D

Q1

Q2

Q3

Q4

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

time (msec)

Shift register

Let Q1 = Q2 = Q3 = Q4 = 0 initially. t Q1 Q2 Q3 Q4

D: 0 1 0 1 1 0 0 0 0

Q1 Q2 Q3

D D Q D Q D Q D Q Q4

Q Q Q Q t

CLK

CLK

D

Q1

Q2

Q3

Q4

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

time (msec)

Shift register

Let Q1 = Q2 = Q3 = Q4 = 0 initially. t Q1 Q2 Q3 Q4

D: 0 1 0 1 1 0 0 0 0

Q1 Q2 Q3

D D Q D Q D Q D Q Q4 1 0 0 0

Q Q Q Q t

CLK

CLK

D

Q1

Q2

Q3

Q4

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

time (msec)

Shift register

Let Q1 = Q2 = Q3 = Q4 = 0 initially. t Q1 Q2 Q3 Q4

D: 0 1 0 1 1 0 0 0 0

Q1 Q2 Q3

D D Q D Q D Q D Q Q4 1 0 0 0

1 1 0 0

Q Q Q Q t

CLK

CLK

D

Q1

Q2

Q3

Q4

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

time (msec)

Shift register

Let Q1 = Q2 = Q3 = Q4 = 0 initially. t Q1 Q2 Q3 Q4

D: 0 1 0 1 1 0 0 0 0

Q1 Q2 Q3

D D Q D Q D Q D Q Q4 1 0 0 0

1 1 0 0

0 1 1 0

Q Q Q Q t

CLK

CLK

D

Q1

Q2

Q3

Q4

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

time (msec)

Shift register

D: 0 1 0 1 1 0 0 0 0

Q1 Q2 Q3

D D Q D Q D Q D Q Q4 1 0 0 0

1 1 0 0

0 1 1 0

Q Q Q Q t

1 0 1 1

CLK

CLK

D

Q1

Q2

Q3

Q4

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

time (msec)

Shift register

D: 0 1 0 1 1 0 0 0 0

Q1 Q2 Q3

D D Q D Q D Q D Q Q4 1 0 0 0

1 1 0 0

0 1 1 0

Q Q Q Q t

1 0 1 1

CLK

0 1 0 1

CLK

D

Q1

Q2

Q3

Q4

**(SEQUEL file: ee101_shift_reg_1.sqproj)
**

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

time (msec)

Shift register

D: 0 1 0 1 1 0 0 0 0

Q1 Q2 Q3

D D Q D Q D Q D Q Q4 1 0 0 0

1 1 0 0

0 1 1 0

Q Q Q Q t

1 0 1 1

CLK

0 1 0 1

CLK

D

Q1

Q2

Q3

Q4

**(SEQUEL file: ee101_shift_reg_1.sqproj)
**

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

time (msec)

*** The data (D) keeps shifting right after each active clock edge.
**

M. B. Patil, IIT Bombay

Parallel transfer between shift registers

A3 A2 A1 A0

D Q D Q D Q D Q

Q Q Q Q

Register A A3 A2 A1 A0

B3 B2 B1 B0 Register B B3 B2 B1 B0

D Q D Q D Q D Q

Q Q Q Q

CLK

**M. B. Patil, IIT Bombay
**

Parallel transfer between shift registers

A3 A2 A1 A0

D Q D Q D Q D Q

Q Q Q Q

Register A A3 A2 A1 A0

B3 B2 B1 B0 Register B B3 B2 B1 B0

D Q D Q D Q D Q

Q Q Q Q

CLK

*** After the active clock edge, the contents of the A register (A3 A2 A1 A0 ) are
**

copied to the B register.

**M. B. Patil, IIT Bombay
**

Bidirectional shift register

M

D0 Q0 D1 Q1 D2 Q2 D3 Q3

DR D Q D Q D Q D Q

Q Q Q Q

DL

M

CLK

**M. B. Patil, IIT Bombay
**

Bidirectional shift register

M

D0 Q0 D1 Q1 D2 Q2 D3 Q3

DR D Q D Q D Q D Q

Q Q Q Q

DL

M

CLK

*** When the mode input (M) is 1, we have
**

D0 = DR , D1 = Q0 , D2 = Q1 , D3 = Q2 .

**M. B. Patil, IIT Bombay
**

Bidirectional shift register

M

D0 Q0 D1 Q1 D2 Q2 D3 Q3

DR D Q D Q D Q D Q

Q Q Q Q

DL

M

CLK

*** When the mode input (M) is 1, we have
**

D0 = DR , D1 = Q0 , D2 = Q1 , D3 = Q2 .

* When the mode input (M) is 0, we have

D0 = Q1 , D1 = Q2 , D2 = Q3 , D3 = DL .

**M. B. Patil, IIT Bombay
**

Bidirectional shift register

M

D0 Q0 D1 Q1 D2 Q2 D3 Q3

DR D Q D Q D Q D Q

Q Q Q Q

DL

M

CLK

*** When the mode input (M) is 1, we have
**

D0 = DR , D1 = Q0 , D2 = Q1 , D3 = Q2 .

* When the mode input (M) is 0, we have

D0 = Q1 , D1 = Q2 , D2 = Q3 , D3 = DL .

* M = 1 → shift right operation.

M = 0 → shift left operation.

**M. B. Patil, IIT Bombay
**

Multiplication using shift and add

1 0 1 1 A3 A2 A1 A0 (decimal 11)

1 1 0 1 B3 B2 B1 B0 (decimal 13)

1 0 1 1 since B0 = 1

0 0 0 0 Z since B1 = 0

0 1 0 1 1 addition

1 0 1 1 Z Z since B2 = 1

1 1 0 1 1 1 addition

1 0 1 1 Z Z Z since B3 = 1

1 0 0 0 1 1 1 1 addition (decimal 143)

**Note that Z = 0. We use Z to denote 0s which are
**

independent of the numbers being multiplied.

Multiplication using shift and add

**1 0 1 1 A3 A2 A1 A0 (decimal 11) Register 2 Register 1
**

1 1 0 1 B3 B2 B1 B0 (decimal 13) Z Z Z Z Z Z Z Z initialize

1 0 1 1 since B0 = 1

0 0 0 0 Z since B1 = 0

0 1 0 1 1 addition

1 0 1 1 Z Z since B2 = 1

1 1 0 1 1 1 addition

1 0 1 1 Z Z Z since B3 = 1

1 0 0 0 1 1 1 1 addition (decimal 143)

**Note that Z = 0. We use Z to denote 0s which are
**

independent of the numbers being multiplied.

Multiplication using shift and add

**1 0 1 1 A3 A2 A1 A0 (decimal 11) Register 2 Register 1
**

1 1 0 1 B3 B2 B1 B0 (decimal 13) Z Z Z Z Z Z Z Z initialize

**1 0 1 1 since B0 = 1 1 0 1 1 load 1011
**

0 0 0 0 Z since B1 = 0 since B0 = 1

0 1 0 1 1 addition

1 0 1 1 Z Z since B2 = 1

1 1 0 1 1 1 addition

1 0 1 1 Z Z Z since B3 = 1

1 0 0 0 1 1 1 1 addition (decimal 143)

**Note that Z = 0. We use Z to denote 0s which are
**

independent of the numbers being multiplied.

Multiplication using shift and add

**1 0 1 1 A3 A2 A1 A0 (decimal 11) Register 2 Register 1
**

1 1 0 1 B3 B2 B1 B0 (decimal 13) Z Z Z Z Z Z Z Z initialize

**1 0 1 1 since B0 = 1 1 0 1 1 load 1011
**

0 0 0 0 Z since B1 = 0 since B0 = 1

1 0 1 1 Z Z Z Z add

0 1 0 1 1 addition

1 0 1 1 Z Z since B2 = 1

1 1 0 1 1 1 addition

1 0 1 1 Z Z Z since B3 = 1

1 0 0 0 1 1 1 1 addition (decimal 143)

**Note that Z = 0. We use Z to denote 0s which are
**

independent of the numbers being multiplied.

Multiplication using shift and add

**1 0 1 1 A3 A2 A1 A0 (decimal 11) Register 2 Register 1
**

1 1 0 1 B3 B2 B1 B0 (decimal 13) Z Z Z Z Z Z Z Z initialize

**1 0 1 1 since B0 = 1 1 0 1 1 load 1011
**

0 0 0 0 Z since B1 = 0 since B0 = 1

1 0 1 1 Z Z Z Z add

0 1 0 1 1 addition

1 0 1 1 Z Z since B2 = 1 Z 1 0 1 1 Z Z Z shift

1 1 0 1 1 1 addition

1 0 1 1 Z Z Z since B3 = 1

1 0 0 0 1 1 1 1 addition (decimal 143)

**Note that Z = 0. We use Z to denote 0s which are
**

independent of the numbers being multiplied.

Multiplication using shift and add

**1 0 1 1 A3 A2 A1 A0 (decimal 11) Register 2 Register 1
**

1 1 0 1 B3 B2 B1 B0 (decimal 13) Z Z Z Z Z Z Z Z initialize

**1 0 1 1 since B0 = 1 1 0 1 1 load 1011
**

0 0 0 0 Z since B1 = 0 since B0 = 1

1 0 1 1 Z Z Z Z add

0 1 0 1 1 addition

1 0 1 1 Z Z since B2 = 1 Z 1 0 1 1 Z Z Z shift

1 1 0 1 1 1 addition load 0000

0 0 0 0

1 0 1 1 Z Z Z since B3 = 1 since B1 = 0

1 0 0 0 1 1 1 1 addition (decimal 143)

**Note that Z = 0. We use Z to denote 0s which are
**

independent of the numbers being multiplied.

Multiplication using shift and add

**1 0 1 1 A3 A2 A1 A0 (decimal 11) Register 2 Register 1
**

1 1 0 1 B3 B2 B1 B0 (decimal 13) Z Z Z Z Z Z Z Z initialize

**1 0 1 1 since B0 = 1 1 0 1 1 load 1011
**

0 0 0 0 Z since B1 = 0 since B0 = 1

1 0 1 1 Z Z Z Z add

0 1 0 1 1 addition

1 0 1 1 Z Z since B2 = 1 Z 1 0 1 1 Z Z Z shift

1 1 0 1 1 1 addition load 0000

0 0 0 0

1 0 1 1 Z Z Z since B3 = 1 since B1 = 0

1 0 0 0 1 1 1 1 addition (decimal 143) 0 1 0 1 1 Z Z Z add

**Note that Z = 0. We use Z to denote 0s which are
**

independent of the numbers being multiplied.

Multiplication using shift and add

**1 0 1 1 A3 A2 A1 A0 (decimal 11) Register 2 Register 1
**

1 1 0 1 B3 B2 B1 B0 (decimal 13) Z Z Z Z Z Z Z Z initialize

**1 0 1 1 since B0 = 1 1 0 1 1 load 1011
**

0 0 0 0 Z since B1 = 0 since B0 = 1

1 0 1 1 Z Z Z Z add

0 1 0 1 1 addition

1 0 1 1 Z Z since B2 = 1 Z 1 0 1 1 Z Z Z shift

1 1 0 1 1 1 addition load 0000

0 0 0 0

1 0 1 1 Z Z Z since B3 = 1 since B1 = 0

1 0 0 0 1 1 1 1 addition (decimal 143) 0 1 0 1 1 Z Z Z add

Z 0 1 0 1 1 Z Z shift

Note that Z = 0. We use Z to denote 0s which are

independent of the numbers being multiplied.

Multiplication using shift and add

**1 0 1 1 A3 A2 A1 A0 (decimal 11) Register 2 Register 1
**

1 1 0 1 B3 B2 B1 B0 (decimal 13) Z Z Z Z Z Z Z Z initialize

**1 0 1 1 since B0 = 1 1 0 1 1 load 1011
**

0 0 0 0 Z since B1 = 0 since B0 = 1

1 0 1 1 Z Z Z Z add

0 1 0 1 1 addition

1 0 1 1 Z Z since B2 = 1 Z 1 0 1 1 Z Z Z shift

1 1 0 1 1 1 addition load 0000

0 0 0 0

1 0 1 1 Z Z Z since B3 = 1 since B1 = 0

1 0 0 0 1 1 1 1 addition (decimal 143) 0 1 0 1 1 Z Z Z add

Z 0 1 0 1 1 Z Z shift

Note that Z = 0. We use Z to denote 0s which are

independent of the numbers being multiplied. 1 0 1 1 load 1011

since B2 = 1

Multiplication using shift and add

**1 0 1 1 A3 A2 A1 A0 (decimal 11) Register 2 Register 1
**

1 1 0 1 B3 B2 B1 B0 (decimal 13) Z Z Z Z Z Z Z Z initialize

**1 0 1 1 since B0 = 1 1 0 1 1 load 1011
**

0 0 0 0 Z since B1 = 0 since B0 = 1

1 0 1 1 Z Z Z Z add

0 1 0 1 1 addition

1 0 1 1 Z Z since B2 = 1 Z 1 0 1 1 Z Z Z shift

1 1 0 1 1 1 addition load 0000

0 0 0 0

1 0 1 1 Z Z Z since B3 = 1 since B1 = 0

1 0 0 0 1 1 1 1 addition (decimal 143) 0 1 0 1 1 Z Z Z add

Z 0 1 0 1 1 Z Z shift

Note that Z = 0. We use Z to denote 0s which are

independent of the numbers being multiplied. 1 0 1 1 load 1011

since B2 = 1

1 1 0 1 1 1 Z Z add

Multiplication using shift and add

**1 0 1 1 A3 A2 A1 A0 (decimal 11) Register 2 Register 1
**

1 1 0 1 B3 B2 B1 B0 (decimal 13) Z Z Z Z Z Z Z Z initialize

**1 0 1 1 since B0 = 1 1 0 1 1 load 1011
**

0 0 0 0 Z since B1 = 0 since B0 = 1

1 0 1 1 Z Z Z Z add

0 1 0 1 1 addition

1 0 1 1 Z Z since B2 = 1 Z 1 0 1 1 Z Z Z shift

1 1 0 1 1 1 addition load 0000

0 0 0 0

1 0 1 1 Z Z Z since B3 = 1 since B1 = 0

1 0 0 0 1 1 1 1 addition (decimal 143) 0 1 0 1 1 Z Z Z add

Z 0 1 0 1 1 Z Z shift

Note that Z = 0. We use Z to denote 0s which are

independent of the numbers being multiplied. 1 0 1 1 load 1011

since B2 = 1

1 1 0 1 1 1 Z Z add

Z 1 1 0 1 1 1 Z shift

Multiplication using shift and add

**1 0 1 1 A3 A2 A1 A0 (decimal 11) Register 2 Register 1
**

1 1 0 1 B3 B2 B1 B0 (decimal 13) Z Z Z Z Z Z Z Z initialize

**1 0 1 1 since B0 = 1 1 0 1 1 load 1011
**

0 0 0 0 Z since B1 = 0 since B0 = 1

1 0 1 1 Z Z Z Z add

0 1 0 1 1 addition

1 0 1 1 Z Z since B2 = 1 Z 1 0 1 1 Z Z Z shift

1 1 0 1 1 1 addition load 0000

0 0 0 0

1 0 1 1 Z Z Z since B3 = 1 since B1 = 0

1 0 0 0 1 1 1 1 addition (decimal 143) 0 1 0 1 1 Z Z Z add

Z 0 1 0 1 1 Z Z shift

Note that Z = 0. We use Z to denote 0s which are

independent of the numbers being multiplied. 1 0 1 1 load 1011

since B2 = 1

1 1 0 1 1 1 Z Z add

Z 1 1 0 1 1 1 Z shift

1 0 1 1 load 1011

since B3 = 1

Multiplication using shift and add

**1 0 1 1 A3 A2 A1 A0 (decimal 11) Register 2 Register 1
**

1 1 0 1 B3 B2 B1 B0 (decimal 13) Z Z Z Z Z Z Z Z initialize

**1 0 1 1 since B0 = 1 1 0 1 1 load 1011
**

0 0 0 0 Z since B1 = 0 since B0 = 1

1 0 1 1 Z Z Z Z add

0 1 0 1 1 addition

1 0 1 1 Z Z since B2 = 1 Z 1 0 1 1 Z Z Z shift

1 1 0 1 1 1 addition load 0000

0 0 0 0

1 0 1 1 Z Z Z since B3 = 1 since B1 = 0

1 0 0 0 1 1 1 1 addition (decimal 143) 0 1 0 1 1 Z Z Z add

Z 0 1 0 1 1 Z Z shift

Note that Z = 0. We use Z to denote 0s which are

independent of the numbers being multiplied. 1 0 1 1 load 1011

since B2 = 1

1 1 0 1 1 1 Z Z add

Z 1 1 0 1 1 1 Z shift

1 0 1 1 load 1011

since B3 = 1

1 0 0 0 1 1 1 1 Z add

Multiplication using shift and add

**1 0 1 1 A3 A2 A1 A0 (decimal 11) Register 2 Register 1
**

1 1 0 1 B3 B2 B1 B0 (decimal 13) Z Z Z Z Z Z Z Z initialize

**1 0 1 1 since B0 = 1 1 0 1 1 load 1011
**

0 0 0 0 Z since B1 = 0 since B0 = 1

1 0 1 1 Z Z Z Z add

0 1 0 1 1 addition

1 0 1 1 Z Z since B2 = 1 Z 1 0 1 1 Z Z Z shift

1 1 0 1 1 1 addition load 0000

0 0 0 0

1 0 1 1 Z Z Z since B3 = 1 since B1 = 0

1 0 0 0 1 1 1 1 addition (decimal 143) 0 1 0 1 1 Z Z Z add

Note that Z = 0. We use Z to denote 0s which are

independent of the numbers being multiplied. 1 0 1 1 load 1011

since B2 = 1

1 1 0 1 1 1 Z Z add

Z 1 1 0 1 1 1 Z shift

1 0 1 1 load 1011

since B3 = 1

1 0 0 0 1 1 1 1 Z add

Z 1 0 0 0 1 1 1 1 shift

**M. B. Patil, IIT Bombay
**

Parallel in-serial out data movement

Load

A3 A2 A1 A0

0 J Sd Q Q3 J Sd Q Q2 J Sd Q Q1 J Sd Q Q0

1 K Rd Q K Rd Q K Rd Q K Rd Q

Clear

CLK

Clear

t

Load

t

CLK

t

Q0 = A0 Q0 = A1 Q0 = A2 Q0 = A3

Parallel in-serial out data movement

Load

A3 A2 A1 A0

0 J Sd Q Q3 J Sd Q Q2 J Sd Q Q1 J Sd Q Q0

1 K Rd Q K Rd Q K Rd Q K Rd Q

Clear

CLK

Clear

t

Load

t

CLK

t

Q0 = A0 Q0 = A1 Q0 = A2 Q0 = A3

*** All flip-flops are cleared in the beginning (with Rd = Clear = 1, Sd = 0).
**

Parallel in-serial out data movement

Load

A3 A2 A1 A0

0 J Sd Q Q3 J Sd Q Q2 J Sd Q Q1 J Sd Q Q0

1 K Rd Q K Rd Q K Rd Q K Rd Q

Clear

CLK

Clear

t

Load

t

CLK

t

Q0 = A0 Q0 = A1 Q0 = A2 Q0 = A3

*** All flip-flops are cleared in the beginning (with Rd = Clear = 1, Sd = 0).
**

* When Load = 1, Sd = Ai , Rd = 0 → Ai gets loaded into the i th flip-flop. (We will assume

that CLK has been made 0 in this initial phase.)

Parallel in-serial out data movement

Load

A3 A2 A1 A0

0 J Sd Q Q3 J Sd Q Q2 J Sd Q Q1 J Sd Q Q0

1 K Rd Q K Rd Q K Rd Q K Rd Q

Clear

CLK

Clear

t

Load

t

CLK

t

Q0 = A0 Q0 = A1 Q0 = A2 Q0 = A3

*** All flip-flops are cleared in the beginning (with Rd = Clear = 1, Sd = 0).
**

* When Load = 1, Sd = Ai , Rd = 0 → Ai gets loaded into the i th flip-flop. (We will assume

that CLK has been made 0 in this initial phase.)

* Subsequently, with every clock pulse, the data shifts right and appears serially at the

output Q0 .

Parallel in-serial out data movement

Load

A3 A2 A1 A0

0 J Sd Q Q3 J Sd Q Q2 J Sd Q Q1 J Sd Q Q0

1 K Rd Q K Rd Q K Rd Q K Rd Q

Clear

CLK

0

Clear

t

Load

t

CLK

t

Q0 = A0 Q0 = A1 Q0 = A2 Q0 = A3

*** All flip-flops are cleared in the beginning (with Rd = Clear = 1, Sd = 0).
**

* When Load = 1, Sd = Ai , Rd = 0 → Ai gets loaded into the i th flip-flop. (We will assume

that CLK has been made 0 in this initial phase.)

* Subsequently, with every clock pulse, the data shifts right and appears serially at the

output Q0 .

Parallel in-serial out data movement

Load

A3 A2 A1 A0

0 J Sd Q Q3 J Sd Q Q2 J Sd Q Q1 J Sd Q Q0

1 K Rd Q K Rd Q K Rd Q K Rd Q

Clear

CLK

0

Clear

t

Load

t

CLK

t

Q0 = A0 Q0 = A1 Q0 = A2 Q0 = A3

*** All flip-flops are cleared in the beginning (with Rd = Clear = 1, Sd = 0).
**

* When Load = 1, Sd = Ai , Rd = 0 → Ai gets loaded into the i th flip-flop. (We will assume

that CLK has been made 0 in this initial phase.)

* Subsequently, with every clock pulse, the data shifts right and appears serially at the

output Q0 .

Parallel in-serial out data movement

Load

A3 A2 A1 A0

0 J Sd Q Q3 J Sd Q Q2 J Sd Q Q1 J Sd Q Q0

1 K Rd Q K Rd Q K Rd Q K Rd Q

Clear

CLK

0 0

Clear

t

Load

t

CLK

t

Q0 = A0 Q0 = A1 Q0 = A2 Q0 = A3

*** All flip-flops are cleared in the beginning (with Rd = Clear = 1, Sd = 0).
**

* When Load = 1, Sd = Ai , Rd = 0 → Ai gets loaded into the i th flip-flop. (We will assume

that CLK has been made 0 in this initial phase.)

* Subsequently, with every clock pulse, the data shifts right and appears serially at the

output Q0 .

Parallel in-serial out data movement

Load

A3 A2 A1 A0

0 J Sd Q Q3 J Sd Q Q2 J Sd Q Q1 J Sd Q Q0

1 K Rd Q K Rd Q K Rd Q K Rd Q

Clear

CLK

0 0 0

Clear

t

Load

t

CLK

t

Q0 = A0 Q0 = A1 Q0 = A2 Q0 = A3

*** All flip-flops are cleared in the beginning (with Rd = Clear = 1, Sd = 0).
**

* When Load = 1, Sd = Ai , Rd = 0 → Ai gets loaded into the i th flip-flop. (We will assume

that CLK has been made 0 in this initial phase.)

* Subsequently, with every clock pulse, the data shifts right and appears serially at the

output Q0 .

Parallel in-serial out data movement

Load

A3 A2 A1 A0

0 J Sd Q Q3 J Sd Q Q2 J Sd Q Q1 J Sd Q Q0

1 K Rd Q K Rd Q K Rd Q K Rd Q

Clear

CLK

0 0 0 0

Clear

t

Load

t

CLK

t

Q0 = A0 Q0 = A1 Q0 = A2 Q0 = A3

*** All flip-flops are cleared in the beginning (with Rd = Clear = 1, Sd = 0).
**

* When Load = 1, Sd = Ai , Rd = 0 → Ai gets loaded into the i th flip-flop. (We will assume

that CLK has been made 0 in this initial phase.)

* Subsequently, with every clock pulse, the data shifts right and appears serially at the

output Q0 .

Parallel in-serial out data movement

Load

A3 A2 A1 A0

0 J Sd Q Q3 J Sd Q Q2 J Sd Q Q1 J Sd Q Q0

1 K Rd Q K Rd Q K Rd Q K Rd Q

Clear

CLK

0 0 0 0 0

Clear

t

Load

t

CLK

t

Q0 = A0 Q0 = A1 Q0 = A2 Q0 = A3

*** All flip-flops are cleared in the beginning (with Rd = Clear = 1, Sd = 0).
**

* When Load = 1, Sd = Ai , Rd = 0 → Ai gets loaded into the i th flip-flop. (We will assume

that CLK has been made 0 in this initial phase.)

* Subsequently, with every clock pulse, the data shifts right and appears serially at the

output Q0 .

M. B. Patil, IIT Bombay

Counters

Q0

1

Q1

k 2 Q2

Clock Counter

3 QN-1

Reset

4 Decoding

logic

State transition diagram General configuration

**M. B. Patil, IIT Bombay
**

Counters

Q0

1

Q1

k 2 Q2

Clock Counter

3 QN-1

Reset

4 Decoding

logic

State transition diagram General configuration

* A counter with k states is called a modulo-k (mod-k) counter.

**M. B. Patil, IIT Bombay
**

Counters

Q0

1

Q1

k 2 Q2

Clock Counter

3 QN-1

Reset

4 Decoding

logic

State transition diagram General configuration

*** A counter with k states is called a modulo-k (mod-k) counter.
**

* A counter can be made with flip-flops, each flip-flop serving as a memory element with two

states (0 or 1).

**M. B. Patil, IIT Bombay
**

Counters

Q0

1

Q1

k 2 Q2

Clock Counter

3 QN-1

Reset

4 Decoding

logic

State transition diagram General configuration

*** A counter with k states is called a modulo-k (mod-k) counter.
**

* A counter can be made with flip-flops, each flip-flop serving as a memory element with two

states (0 or 1).

* If there are N flip-flops in a counter, there are 2N possible states (since each flip-flop can

have Q = 0 or Q = 1). It is possible to exclude some of these states.

→ N flip-flops can be used to make a mod-k counter with k ≤ 2N .

**M. B. Patil, IIT Bombay
**

Counters

Q0

1

Q1

k 2 Q2

Clock Counter

3 QN-1

Reset

4 Decoding

logic

State transition diagram General configuration

*** A counter with k states is called a modulo-k (mod-k) counter.
**

* A counter can be made with flip-flops, each flip-flop serving as a memory element with two

states (0 or 1).

* If there are N flip-flops in a counter, there are 2N possible states (since each flip-flop can

have Q = 0 or Q = 1). It is possible to exclude some of these states.

→ N flip-flops can be used to make a mod-k counter with k ≤ 2N .

* Typically, a reset facility is also provided, which can be used to force a certain state to

initialize the counter.

**M. B. Patil, IIT Bombay
**

Counters

Q0

1

Q1

k 2 Q2

Clock Counter

3 QN-1

Reset

4 Decoding

logic

State transition diagram General configuration

1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1

CLK

t

X

t

8T

X is 1 for state 3; else, it is 0.

**M. B. Patil, IIT Bombay
**

Counters

Q0

1

Q1

k 2 Q2

Clock Counter

3 QN-1

Reset

4 Decoding

logic

State transition diagram General configuration

1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1

CLK

t

X

t

8T

X is 1 for state 3; else, it is 0.

*** The counter outputs (i.e., the flip-flop outputs, Q0 , Q1 , · · · QN−1 ) can be decoded using
**

appropriate logic.

**M. B. Patil, IIT Bombay
**

Counters

Q0

1

Q1

k 2 Q2

Clock Counter

3 QN-1

Reset

4 Decoding

logic

State transition diagram General configuration

1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1

CLK

t

X

t

8T

X is 1 for state 3; else, it is 0.

*** The counter outputs (i.e., the flip-flop outputs, Q0 , Q1 , · · · QN−1 ) can be decoded using
**

appropriate logic.

* In particular, it is possible to have a decoder output (say, X ) which is 1 only for state i, and

0 otherwise.

→ For k clock pulses, we get a single pulse at X , i.e., the clock frequency has been divided

by k. For this reason, a mod-k counter is also called a divide-by-k counter.

M. B. Patil, IIT Bombay

A binay ripple counter

1

Q0 Q1 Q2

J Q J Q J Q

CLK FF0 FF1 FF2

K Q K Q K Q

CLK

t

Q0

t

Q1

t

Q2

t

A binay ripple counter

1

Q0 Q1 Q2

J Q J Q J Q

CLK FF0 FF1 FF2

K Q K Q K Q

CLK

t

Q0

t

Q1

t

Q2

t

*** J = K = 1 for all flip-flops. Let Q0 = Q1 = Q2 = 0 initially.
**

A binay ripple counter

1

Q0 Q1 Q2

J Q J Q J Q

CLK FF0 FF1 FF2

K Q K Q K Q

CLK

t

Q0

t

Q1

t

Q2

t

*** J = K = 1 for all flip-flops. Let Q0 = Q1 = Q2 = 0 initially.
**

* Since J = K = 1, each flip-flop will toggle when an active (in this case, negative) clock edge

arrives.

A binay ripple counter

1

Q0 Q1 Q2

J Q J Q J Q

CLK FF0 FF1 FF2

K Q K Q K Q

CLK

t

Q0

t

Q1

t

Q2

t

*** J = K = 1 for all flip-flops. Let Q0 = Q1 = Q2 = 0 initially.
**

* Since J = K = 1, each flip-flop will toggle when an active (in this case, negative) clock edge

arrives.

* For FF1 and FF2, Q0 and Q1 , respectively, provide the clock.

A binay ripple counter

1

Q0 Q1 Q2

J Q J Q J Q

CLK FF0 FF1 FF2

K Q K Q K Q

CLK

t

Q0

t

Q1

t

Q2

t

*** J = K = 1 for all flip-flops. Let Q0 = Q1 = Q2 = 0 initially.
**

* Since J = K = 1, each flip-flop will toggle when an active (in this case, negative) clock edge

arrives.

* For FF1 and FF2, Q0 and Q1 , respectively, provide the clock.

A binay ripple counter

1

Q0 Q1 Q2

J Q J Q J Q

CLK FF0 FF1 FF2

K Q K Q K Q

CLK

t

Q0

t

Q1

t

Q2

t

*** J = K = 1 for all flip-flops. Let Q0 = Q1 = Q2 = 0 initially.
**

* Since J = K = 1, each flip-flop will toggle when an active (in this case, negative) clock edge

arrives.

* For FF1 and FF2, Q0 and Q1 , respectively, provide the clock.

A binay ripple counter

1

Q0 Q1 Q2

J Q J Q J Q

CLK FF0 FF1 FF2

K Q K Q K Q

CLK

t

Q0

t

Q1

t

Q2

t

*** J = K = 1 for all flip-flops. Let Q0 = Q1 = Q2 = 0 initially.
**

* Since J = K = 1, each flip-flop will toggle when an active (in this case, negative) clock edge

arrives.

* For FF1 and FF2, Q0 and Q1 , respectively, provide the clock.

A binay ripple counter

1

Q0 Q1 Q2

J Q J Q J Q

CLK FF0 FF1 FF2 Q2 Q1 Q0

K Q K Q K Q 0 0 0

0 0 1

0 1 0

CLK

0 1 1

t 1 0 0

Q0 1 0 1

1 1 0

t

1 1 1

Q1

0 0 0 repeats

t

Q2

t

*** J = K = 1 for all flip-flops. Let Q0 = Q1 = Q2 = 0 initially.
**

* Since J = K = 1, each flip-flop will toggle when an active (in this case, negative) clock edge

arrives.

* For FF1 and FF2, Q0 and Q1 , respectively, provide the clock.

A binay ripple counter

1

Q0 Q1 Q2

J Q J Q J Q

CLK FF0 FF1 FF2 Q2 Q1 Q0

K Q K Q K Q 0 0 0

0 0 1

0 1 0

CLK

0 1 1

t 1 0 0

Q0 1 0 1

1 1 0

t

1 1 1

Q1

0 0 0 repeats

t

Q2

t

*** J = K = 1 for all flip-flops. Let Q0 = Q1 = Q2 = 0 initially.
**

* Since J = K = 1, each flip-flop will toggle when an active (in this case, negative) clock edge

arrives.

* For FF1 and FF2, Q0 and Q1 , respectively, provide the clock.

* Note that the direct inputs Sd and Rd (not shown) are assumed to be Sd = Rd = 0 for all

flip-flops, allowing normal flip-flip operation.

M. B. Patil, IIT Bombay

A binay ripple counter

1

Q0 Q1 Q2

J Q J Q J Q

CLK FF0 FF1 FF2 Q2 Q1 Q0

K Q K Q K Q 0 0 0

0 0 1

0 1 0

CLK

0 1 1

t 1 0 0

Q0 1 0 1

1 1 0

t

1 1 1

Q1

0 0 0 repeats

t

Q2

t

**M. B. Patil, IIT Bombay
**

A binay ripple counter

1

Q0 Q1 Q2

J Q J Q J Q

CLK FF0 FF1 FF2 Q2 Q1 Q0

K Q K Q K Q 0 0 0

0 0 1

0 1 0

CLK

0 1 1

t 1 0 0

Q0 1 0 1

1 1 0

t

1 1 1

Q1

0 0 0 repeats

t

Q2

t

*** The counter has 8 states, Q2 Q1 Q0 = 000, 001, 010, 011, 100, 101, 110, 111.
**

→ it is a mod-8 counter. In particular, it is a binary, mod-8, up counter (since it counts up

from 000 to 111).

**M. B. Patil, IIT Bombay
**

A binay ripple counter

1

Q0 Q1 Q2

J Q J Q J Q

CLK FF0 FF1 FF2 Q2 Q1 Q0

K Q K Q K Q 0 0 0

0 0 1

0 1 0

CLK

0 1 1

t 1 0 0

Q0 1 0 1

1 1 0

t

1 1 1

Q1

0 0 0 repeats

t

Q2

t

*** The counter has 8 states, Q2 Q1 Q0 = 000, 001, 010, 011, 100, 101, 110, 111.
**

→ it is a mod-8 counter. In particular, it is a binary, mod-8, up counter (since it counts up

from 000 to 111).

* If the clock frequency is fc , the frequency at the Q0 , Q1 , Q2 outputs is fc /2, fc /4, fc /8,

respectively. For this counter, therefore, div-by-2, div-by-4, div-by-8 outputs are already

available, without requring decoding logic.

**M. B. Patil, IIT Bombay
**

A binay ripple counter

1

Q0 Q1 Q2

J Q J Q J Q

CLK FF0 FF1 FF2 Q2 Q1 Q0

K Q K Q K Q 0 0 0

0 0 1

0 1 0

CLK

0 1 1

t 1 0 0

Q0 1 0 1

1 1 0

t

1 1 1

Q1

0 0 0 repeats

t

Q2

t

*** The counter has 8 states, Q2 Q1 Q0 = 000, 001, 010, 011, 100, 101, 110, 111.
**

→ it is a mod-8 counter. In particular, it is a binary, mod-8, up counter (since it counts up

from 000 to 111).

* If the clock frequency is fc , the frequency at the Q0 , Q1 , Q2 outputs is fc /2, fc /4, fc /8,

respectively. For this counter, therefore, div-by-2, div-by-4, div-by-8 outputs are already

available, without requring decoding logic.

* This type of counter is called a “ripple” counter since the clock transitions ripple through

the flip-flops.

M. B. Patil, IIT Bombay

A binay ripple counter

1

Q0 Q1 Q2

J Q J Q J Q

CLK FF0 FF1 FF2 Q2 Q1 Q0

K Q K Q K Q 0 0 0

1 1 1

1 1 0

CLK

1 0 1

t 1 0 0

Q0 0 1 1

0 1 0

t

0 0 1

Q1

0 0 0 repeats

t

Q2

t

**M. B. Patil, IIT Bombay
**

A binay ripple counter

1

Q0 Q1 Q2

J Q J Q J Q

CLK FF0 FF1 FF2 Q2 Q1 Q0

K Q K Q K Q 0 0 0

1 1 1

1 1 0

CLK

1 0 1

t 1 0 0

Q0 0 1 1

0 1 0

t

0 0 1

Q1

0 0 0 repeats

t

Q2

t

*** If positive edge-triggered flip-flops are used, we get a binary down counter (counting down
**

from 1111 to 0000).

**M. B. Patil, IIT Bombay
**

Binay ripple counters

1

Q0 Q1 Q2

J Q J Q J Q

CLK FF0 FF1 FF2

K Q K Q K Q

1

Q0 Q1 Q2

J Q J Q J Q

CLK FF0 FF1 FF2

K Q K Q K Q

*** Home work: Sketch the waveforms (CLK, Q0 , Q1 , Q2 ), and tabulate the counter states in
**

each case.

**M. B. Patil, IIT Bombay
**

Up-down binay ripple counters

1

M

J Q J Q J Q

Q0 Q1 Q2

CLK FF0 FF1 FF2

K Q K Q K Q

M

M=1 M=0

CLK CLK

t t

Q0 Q0

t t

Q1 Q1

t t

Q2 Q2

t t

**M. B. Patil, IIT Bombay
**

Up-down binay ripple counters

1

M

J Q J Q J Q

Q0 Q1 Q2

CLK FF0 FF1 FF2

K Q K Q K Q

M

M=1 M=0

CLK CLK

t t

Q0 Q0

t t

Q1 Q1

t t

Q2 Q2

t t

*** When Mode (M) = 1, the counter counts up; else, it counts down.
**

(SEQUEL file: ee101 counter 3.sqproj)

**M. B. Patil, IIT Bombay
**

Decade counter using direct inputs

0

1

Sd Q0 Sd Q1 Sd Q2 Sd Q3

J Q J Q J Q J Q

CLK FF0 FF1 FF2 FF3

K Rd Q K Rd Q K Rd Q K Rd Q

Q3 Q2 Q1 Q0

0 0 0 0

Q0 0 0 0 1

0 0 1 0

0 0 1 1

Q1 0 1 0 0

0 1 0 1

0 1 1 0

Q2

0 1 1 1

1 0 0 0

Q3 1 0 0 1

0 0 0 0 repeats

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8

time (msec)

**M. B. Patil, IIT Bombay
**

Decade counter using direct inputs

0

1

Sd Q0 Sd Q1 Sd Q2 Sd Q3

J Q J Q J Q J Q

CLK FF0 FF1 FF2 FF3

K Rd Q K Rd Q K Rd Q K Rd Q

Q3 Q2 Q1 Q0

0 0 0 0

Q0 0 0 0 1

0 0 1 0

0 0 1 1

Q1 0 1 0 0

0 1 0 1

0 1 1 0

Q2

0 1 1 1

1 0 0 0

Q3 1 0 0 1

0 0 0 0 repeats

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8

time (msec)

*** When the counter reaches Q3 Q2 Q1 Q0 = 1010 (i.e., decmial 10), Q3 Q1 = 1, and the flip-flops
**

are cleared to Q3 Q2 Q1 Q0 = 0000.

**M. B. Patil, IIT Bombay
**

Decade counter using direct inputs

0

1

Sd Q0 Sd Q1 Sd Q2 Sd Q3

J Q J Q J Q J Q

CLK FF0 FF1 FF2 FF3

K Rd Q K Rd Q K Rd Q K Rd Q

Q3 Q2 Q1 Q0

0 0 0 0

Q0 0 0 0 1

0 0 1 0

0 0 1 1

Q1 0 1 0 0

0 1 0 1

0 1 1 0

Q2

0 1 1 1

1 0 0 0

Q3 1 0 0 1

0 0 0 0 repeats

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8

time (msec)

*** When the counter reaches Q3 Q2 Q1 Q0 = 1010 (i.e., decmial 10), Q3 Q1 = 1, and the flip-flops
**

are cleared to Q3 Q2 Q1 Q0 = 0000.

* The counter counts from 0000 (decimal 0) to 1001 (decimal 9) → “decade counter.”

(SEQUEL file: ee101 counter 5.sqproj)

M. B. Patil, IIT Bombay

A synchronous counter

1

J Q J Q J Q J Q

Q0 Q1 Q2 Q3

FF0 FF1 FF2 FF3

K Q K Q K Q K Q

CLK

CLK

t

Q0

t

Q1

t

Q2

t

Q3

t

A synchronous counter

1

J Q J Q J Q J Q

Q0 Q1 Q2 Q3

FF0 FF1 FF2 FF3

K Q K Q K Q K Q

CLK

CLK

t

Q0

t

Q1

t

Q2

t

Q3

t

*** Since all flip-flops are driven by the same clock, the counter is called a “synchronous”
**

counter.

A synchronous counter

1

J Q J Q J Q J Q

Q0 Q1 Q2 Q3

FF0 FF1 FF2 FF3

K Q K Q K Q K Q

CLK

CLK

t

Q0

t

Q1

t

Q2

t

Q3

t

*** Since all flip-flops are driven by the same clock, the counter is called a “synchronous”
**

counter.

* J0 = K0 = 1, J1 = K1 = Q0 , J2 = K2 = Q1 Q0 , J3 = K3 = Q2 Q1 Q0 .

A synchronous counter

1

J Q J Q J Q J Q

Q0 Q1 Q2 Q3

FF0 FF1 FF2 FF3

K Q K Q K Q K Q

CLK

CLK

t

Q0

t

Q1

t

Q2

t

Q3

t

*** Since all flip-flops are driven by the same clock, the counter is called a “synchronous”
**

counter.

* J0 = K0 = 1, J1 = K1 = Q0 , J2 = K2 = Q1 Q0 , J3 = K3 = Q2 Q1 Q0 .

* FF0 toggles at every active edge.

FF1 toggles if Q0 = 1 (just before the active clock edge); else, it retains its previous state.

Similar comments apply to FF2 and FF3.

A synchronous counter

1

J Q J Q J Q J Q

Q0 Q1 Q2 Q3

FF0 FF1 FF2 FF3

K Q K Q K Q K Q

CLK

CLK

t

Q0

t

Q1

t

Q2

t

Q3

t

*** Since all flip-flops are driven by the same clock, the counter is called a “synchronous”
**

counter.

* J0 = K0 = 1, J1 = K1 = Q0 , J2 = K2 = Q1 Q0 , J3 = K3 = Q2 Q1 Q0 .

* FF0 toggles at every active edge.

FF1 toggles if Q0 = 1 (just before the active clock edge); else, it retains its previous state.

Similar comments apply to FF2 and FF3.

A synchronous counter

1

J Q J Q J Q J Q

Q0 Q1 Q2 Q3

FF0 FF1 FF2 FF3

K Q K Q K Q K Q

CLK

CLK

t

Q0

t

Q1

t

Q2

t

Q3

t

*** Since all flip-flops are driven by the same clock, the counter is called a “synchronous”
**

counter.

* J0 = K0 = 1, J1 = K1 = Q0 , J2 = K2 = Q1 Q0 , J3 = K3 = Q2 Q1 Q0 .

* FF0 toggles at every active edge.

FF1 toggles if Q0 = 1 (just before the active clock edge); else, it retains its previous state.

Similar comments apply to FF2 and FF3.

A synchronous counter

1

J Q J Q J Q J Q

Q0 Q1 Q2 Q3

FF0 FF1 FF2 FF3

K Q K Q K Q K Q

CLK

CLK

t

Q0

t

Q1

t

Q2

t

Q3

t

*** Since all flip-flops are driven by the same clock, the counter is called a “synchronous”
**

counter.

* J0 = K0 = 1, J1 = K1 = Q0 , J2 = K2 = Q1 Q0 , J3 = K3 = Q2 Q1 Q0 .

* FF0 toggles at every active edge.

FF1 toggles if Q0 = 1 (just before the active clock edge); else, it retains its previous state.

Similar comments apply to FF2 and FF3.

A synchronous counter

1

J Q J Q J Q J Q

Q0 Q1 Q2 Q3

FF0 FF1 FF2 FF3

K Q K Q K Q K Q

CLK

CLK

t

Q0

t

Q1

t

Q2

t

Q3

t

*** Since all flip-flops are driven by the same clock, the counter is called a “synchronous”
**

counter.

* J0 = K0 = 1, J1 = K1 = Q0 , J2 = K2 = Q1 Q0 , J3 = K3 = Q2 Q1 Q0 .

* FF0 toggles at every active edge.

FF1 toggles if Q0 = 1 (just before the active clock edge); else, it retains its previous state.

Similar comments apply to FF2 and FF3.

A synchronous counter

1

J Q J Q J Q J Q

Q0 Q1 Q2 Q3

FF0 FF1 FF2 FF3

K Q K Q K Q K Q

CLK

CLK

t

Q0

t

Q1

t

Q2

t

Q3

t

*** Since all flip-flops are driven by the same clock, the counter is called a “synchronous”
**

counter.

* J0 = K0 = 1, J1 = K1 = Q0 , J2 = K2 = Q1 Q0 , J3 = K3 = Q2 Q1 Q0 .

* FF0 toggles at every active edge.

FF1 toggles if Q0 = 1 (just before the active clock edge); else, it retains its previous state.

Similar comments apply to FF2 and FF3.

* From the waveforms, we see that it is a binary up counter.

M. B. Patil, IIT Bombay

Design of synchronous counters

CLK J K Qn+1

J Q Qn

0 0

CLK 0 1 0

K Q 1 0 1

1 1 Qn

Design of synchronous counters

CLK J K Qn+1 CLK Qn Qn+1 J K

J Q Qn

0 0

CLK 0 1 0

K Q 1 0 1

1 1 Qn

*** Consider the reverse problem: We are given Qn and the next desired state (Qn+1 ). What
**

should J and K be in order to make that happen?

Design of synchronous counters

CLK J K Qn+1 CLK Qn Qn+1 J K

J Q Qn

0 0

CLK 0 1 0

K Q 1 0 1

1 1 Qn

*** Consider the reverse problem: We are given Qn and the next desired state (Qn+1 ). What
**

should J and K be in order to make that happen?

* Qn = 0, Qn+1 = 0: We can either force Qn+1 = 0 with J = 0, K = 1, or let Qn+1 = Qn = 0 by

making J = 0, K = 0.

Design of synchronous counters

CLK J K Qn+1 CLK Qn Qn+1 J K

J Q Qn

0 0

CLK 0 1 0

K Q 1 0 1

1 1 Qn

*** Consider the reverse problem: We are given Qn and the next desired state (Qn+1 ). What
**

should J and K be in order to make that happen?

* Qn = 0, Qn+1 = 0: We can either force Qn+1 = 0 with J = 0, K = 1, or let Qn+1 = Qn = 0 by

making J = 0, K = 0.

→ J = 0, K = X (i.e., K can be 0 or 1).

Design of synchronous counters

CLK J K Qn+1 CLK Qn Qn+1 J K

J Q Qn

0 0 0 0 0 X

CLK 0 1 0

K Q 1 0 1

1 1 Qn

*** Consider the reverse problem: We are given Qn and the next desired state (Qn+1 ). What
**

should J and K be in order to make that happen?

* Qn = 0, Qn+1 = 0: We can either force Qn+1 = 0 with J = 0, K = 1, or let Qn+1 = Qn = 0 by

making J = 0, K = 0.

→ J = 0, K = X (i.e., K can be 0 or 1).

Design of synchronous counters

CLK J K Qn+1 CLK Qn Qn+1 J K

J Q Qn

0 0 0 0 0 X

CLK 0 1 0

K Q 1 0 1

1 1 Qn

*** Consider the reverse problem: We are given Qn and the next desired state (Qn+1 ). What
**

should J and K be in order to make that happen?

* Qn = 0, Qn+1 = 0: We can either force Qn+1 = 0 with J = 0, K = 1, or let Qn+1 = Qn = 0 by

making J = 0, K = 0.

→ J = 0, K = X (i.e., K can be 0 or 1).

* Similarly, work out the other entries in the table.

Design of synchronous counters

CLK J K Qn+1 CLK Qn Qn+1 J K

J Q Qn

0 0 0 0 0 X

CLK 0 1 0 0 1 1 X

K Q 1 0 1 1 0 X 1

1 1 Qn 1 1 X 0

*** Consider the reverse problem: We are given Qn and the next desired state (Qn+1 ). What
**

should J and K be in order to make that happen?

* Qn = 0, Qn+1 = 0: We can either force Qn+1 = 0 with J = 0, K = 1, or let Qn+1 = Qn = 0 by

making J = 0, K = 0.

→ J = 0, K = X (i.e., K can be 0 or 1).

* Similarly, work out the other entries in the table.

Design of synchronous counters

CLK J K Qn+1 CLK Qn Qn+1 J K

J Q Qn

0 0 0 0 0 X

CLK 0 1 0 0 1 1 X

K Q 1 0 1 1 0 X 1

1 1 Qn 1 1 X 0

*** Consider the reverse problem: We are given Qn and the next desired state (Qn+1 ). What
**

should J and K be in order to make that happen?

* Qn = 0, Qn+1 = 0: We can either force Qn+1 = 0 with J = 0, K = 1, or let Qn+1 = Qn = 0 by

making J = 0, K = 0.

→ J = 0, K = X (i.e., K can be 0 or 1).

* Similarly, work out the other entries in the table.

* The table for a negative edge-triggered flip-flop would be identical excpet for the active

edge.

**M. B. Patil, IIT Bombay
**

Design of synchronous counters

state Q2 Q1 Q0 CLK Qn Qn+1 J K

J2 Q2 J1 Q1 J0 Q0

1 0 0 0 J Q J Q J Q 0 0 0 X

2 0 0 1 0 1 1 X

3 0 1 0

1 0 X 1

4 0 1 1 K Q K Q K Q

K2 K1 K0

5 1 0 0 1 1 X 0

CLK

1 0 0 0 repeats

Design a synchronous mod-5 counter with the given state transition table.

**M. B. Patil, IIT Bombay
**

Design of synchronous counters

state Q2 Q1 Q0 CLK Qn Qn+1 J K

J2 Q2 J1 Q1 J0 Q0

1 0 0 0 J Q J Q J Q 0 0 0 X

2 0 0 1 0 1 1 X

3 0 1 0

1 0 X 1

4 0 1 1 K Q K Q K Q

K2 K1 K0

5 1 0 0 1 1 X 0

CLK

1 0 0 0 repeats

**Design a synchronous mod-5 counter with the given state transition table.
**

Outline of method:

**M. B. Patil, IIT Bombay
**

Design of synchronous counters

state Q2 Q1 Q0 CLK Qn Qn+1 J K

J2 Q2 J1 Q1 J0 Q0

1 0 0 0 J Q J Q J Q 0 0 0 X

2 0 0 1 0 1 1 X

3 0 1 0

1 0 X 1

4 0 1 1 K Q K Q K Q

K2 K1 K0

5 1 0 0 1 1 X 0

CLK

1 0 0 0 repeats

**Design a synchronous mod-5 counter with the given state transition table.
**

Outline of method:

* State 1 → State 2 means

Q2 : 0 → 0,

Q1 : 0 → 0,

Q0 : 0 → 1.

**M. B. Patil, IIT Bombay
**

Design of synchronous counters

J2 Q2 J1 Q1 J0 Q0

1 0 0 0 J Q J Q J Q 0 0 0 X

2 0 0 1 0 1 1 X

3 0 1 0

1 0 X 1

4 0 1 1 K Q K Q K Q

K2 K1 K0

5 1 0 0 1 1 X 0

CLK

1 0 0 0 repeats

**Design a synchronous mod-5 counter with the given state transition table.
**

Outline of method:

* State 1 → State 2 means

Q2 : 0 → 0,

Q1 : 0 → 0,

Q0 : 0 → 1.

* Refer to the right table. For Q2 : 0 → 0, we must have J2 = 0, K2 = X , and so on.

**M. B. Patil, IIT Bombay
**

Design of synchronous counters

J2 Q2 J1 Q1 J0 Q0

1 0 0 0 J Q J Q J Q 0 0 0 X

2 0 0 1 0 1 1 X

3 0 1 0

1 0 X 1

4 0 1 1 K Q K Q K Q

K2 K1 K0

5 1 0 0 1 1 X 0

CLK

1 0 0 0 repeats

**Design a synchronous mod-5 counter with the given state transition table.
**

Outline of method:

* State 1 → State 2 means

Q2 : 0 → 0,

Q1 : 0 → 0,

Q0 : 0 → 1.

* Refer to the right table. For Q2 : 0 → 0, we must have J2 = 0, K2 = X , and so on.

* When we cover all transitions in the left table, we have the truth tables for J0 , K0 , J1 , K1 ,

J2 , K2 in terms of Q1 , Q2 , Q3 .

**M. B. Patil, IIT Bombay
**

Design of synchronous counters

J2 Q2 J1 Q1 J0 Q0

1 0 0 0 J Q J Q J Q 0 0 0 X

2 0 0 1 0 1 1 X

3 0 1 0

1 0 X 1

4 0 1 1 K Q K Q K Q

K2 K1 K0

5 1 0 0 1 1 X 0

CLK

1 0 0 0 repeats

**Design a synchronous mod-5 counter with the given state transition table.
**

Outline of method:

* State 1 → State 2 means

Q2 : 0 → 0,

Q1 : 0 → 0,

Q0 : 0 → 1.

* Refer to the right table. For Q2 : 0 → 0, we must have J2 = 0, K2 = X , and so on.

* When we cover all transitions in the left table, we have the truth tables for J0 , K0 , J1 , K1 ,

J2 , K2 in terms of Q1 , Q2 , Q3 .

* The last step is to come up with suitable functions for J0 , K0 , J1 , K1 , J2 , K2 in terms of Q1 ,

Q2 , Q3 . This can be done with K-maps. (If the number of flip-flops is more than 4, other

techniques can be employed.)

**M. B. Patil, IIT Bombay
**

Design of synchronous counters

state Q2 Q1 Q0 J2 K2 J1 K1 J0 K0

CLK Qn Qn+1 J K

1 0 0 0

0 0 0 X

2 0 0 1

3 0 1 0 0 1 1 X

4 0 1 1 1 0 X 1

5 1 0 0

1 1 X 0

1 0 0 0

Design of synchronous counters

state Q2 Q1 Q0 J2 K2 J1 K1 J0 K0

CLK Qn Qn+1 J K

1 0 0 0

0 0 0 X

2 0 0 1

3 0 1 0 0 1 1 X

4 0 1 1 1 0 X 1

5 1 0 0

1 1 X 0

1 0 0 0

Design of synchronous counters

state Q2 Q1 Q0 J2 K2 J1 K1 J0 K0

CLK Qn Qn+1 J K

1 0 0 0 0 X

0 0 0 X

2 0 0 1

3 0 1 0 0 1 1 X

4 0 1 1 1 0 X 1

5 1 0 0

1 1 X 0

1 0 0 0

Design of synchronous counters

state Q2 Q1 Q0 J2 K2 J1 K1 J0 K0

CLK Qn Qn+1 J K

1 0 0 0 0 X 0 X

0 0 0 X

2 0 0 1

3 0 1 0 0 1 1 X

4 0 1 1 1 0 X 1

5 1 0 0

1 1 X 0

1 0 0 0

Design of synchronous counters

state Q2 Q1 Q0 J2 K2 J1 K1 J0 K0

CLK Qn Qn+1 J K

1 0 0 0 0 X 0 X 1 X

0 0 0 X

2 0 0 1

3 0 1 0 0 1 1 X

4 0 1 1 1 0 X 1

5 1 0 0

1 1 X 0

1 0 0 0

Design of synchronous counters

state Q2 Q1 Q0 J2 K2 J1 K1 J0 K0

CLK Qn Qn+1 J K

1 0 0 0 0 X 0 X 1 X

0 0 0 X

2 0 0 1

3 0 1 0 0 1 1 X

4 0 1 1 1 0 X 1

5 1 0 0

1 1 X 0

1 0 0 0

Design of synchronous counters

state Q2 Q1 Q0 J2 K2 J1 K1 J0 K0

CLK Qn Qn+1 J K

1 0 0 0 0 X 0 X 1 X

0 0 0 X

2 0 0 1 0 X

3 0 1 0 0 1 1 X

4 0 1 1 1 0 X 1

5 1 0 0

1 1 X 0

1 0 0 0

Design of synchronous counters

state Q2 Q1 Q0 J2 K2 J1 K1 J0 K0

CLK Qn Qn+1 J K

1 0 0 0 0 X 0 X 1 X

0 0 0 X

2 0 0 1 0 X 1 X

3 0 1 0 0 1 1 X

4 0 1 1 1 0 X 1

5 1 0 0

1 1 X 0

1 0 0 0

Design of synchronous counters

state Q2 Q1 Q0 J2 K2 J1 K1 J0 K0

CLK Qn Qn+1 J K

1 0 0 0 0 X 0 X 1 X

0 0 0 X

2 0 0 1 0 X 1 X X 1

3 0 1 0 0 1 1 X

4 0 1 1 1 0 X 1

5 1 0 0

1 1 X 0

1 0 0 0

Design of synchronous counters

state Q2 Q1 Q0 J2 K2 J1 K1 J0 K0

CLK Qn Qn+1 J K

1 0 0 0 0 X 0 X 1 X

0 0 0 X

2 0 0 1 0 X 1 X X 1

3 0 1 0 0 1 1 X

4 0 1 1 1 0 X 1

5 1 0 0

1 1 X 0

1 0 0 0

Design of synchronous counters

state Q2 Q1 Q0 J2 K2 J1 K1 J0 K0

CLK Qn Qn+1 J K

1 0 0 0 0 X 0 X 1 X

0 0 0 X

2 0 0 1 0 X 1 X X 1

3 0 1 0 0 X 0 1 1 X

4 0 1 1 1 0 X 1

5 1 0 0

1 1 X 0

1 0 0 0

Design of synchronous counters

state Q2 Q1 Q0 J2 K2 J1 K1 J0 K0

CLK Qn Qn+1 J K

1 0 0 0 0 X 0 X 1 X

0 0 0 X

2 0 0 1 0 X 1 X X 1

3 0 1 0 0 X X 0 0 1 1 X

4 0 1 1 1 0 X 1

5 1 0 0

1 1 X 0

1 0 0 0

Design of synchronous counters

state Q2 Q1 Q0 J2 K2 J1 K1 J0 K0

CLK Qn Qn+1 J K

1 0 0 0 0 X 0 X 1 X

0 0 0 X

2 0 0 1 0 X 1 X X 1

3 0 1 0 0 X X 0 1 X 0 1 1 X

4 0 1 1 1 0 X 1

5 1 0 0

1 1 X 0

1 0 0 0

Design of synchronous counters

state Q2 Q1 Q0 J2 K2 J1 K1 J0 K0

CLK Qn Qn+1 J K

1 0 0 0 0 X 0 X 1 X

0 0 0 X

2 0 0 1 0 X 1 X X 1

3 0 1 0 0 X X 0 1 X 0 1 1 X

4 0 1 1 1 0 X 1

5 1 0 0

1 1 X 0

1 0 0 0

Design of synchronous counters

state Q2 Q1 Q0 J2 K2 J1 K1 J0 K0

CLK Qn Qn+1 J K

1 0 0 0 0 X 0 X 1 X

0 0 0 X

2 0 0 1 0 X 1 X X 1

3 0 1 0 0 X X 0 1 X 0 1 1 X

4 0 1 1 1 X 1 0 X 1

5 1 0 0

1 1 X 0

1 0 0 0

Design of synchronous counters

state Q2 Q1 Q0 J2 K2 J1 K1 J0 K0

CLK Qn Qn+1 J K

1 0 0 0 0 X 0 X 1 X

0 0 0 X

2 0 0 1 0 X 1 X X 1

3 0 1 0 0 X X 0 1 X 0 1 1 X

4 0 1 1 1 X X 1 1 0 X 1

5 1 0 0

1 1 X 0

1 0 0 0

Design of synchronous counters

state Q2 Q1 Q0 J2 K2 J1 K1 J0 K0

CLK Qn Qn+1 J K

1 0 0 0 0 X 0 X 1 X

0 0 0 X

2 0 0 1 0 X 1 X X 1

3 0 1 0 0 X X 0 1 X 0 1 1 X

4 0 1 1 1 X X 1 X 1 1 0 X 1

5 1 0 0

1 1 X 0

1 0 0 0

Design of synchronous counters

state Q2 Q1 Q0 J2 K2 J1 K1 J0 K0

CLK Qn Qn+1 J K

1 0 0 0 0 X 0 X 1 X

0 0 0 X

2 0 0 1 0 X 1 X X 1

3 0 1 0 0 X X 0 1 X 0 1 1 X

4 0 1 1 1 X X 1 X 1 1 0 X 1

5 1 0 0

1 1 X 0

1 0 0 0

Design of synchronous counters

state Q2 Q1 Q0 J2 K2 J1 K1 J0 K0

CLK Qn Qn+1 J K

1 0 0 0 0 X 0 X 1 X

0 0 0 X

2 0 0 1 0 X 1 X X 1

3 0 1 0 0 X X 0 1 X 0 1 1 X

4 0 1 1 1 X X 1 X 1 1 0 X 1

5 1 0 0 X 1

1 1 X 0

1 0 0 0

Design of synchronous counters

state Q2 Q1 Q0 J2 K2 J1 K1 J0 K0

CLK Qn Qn+1 J K

1 0 0 0 0 X 0 X 1 X

0 0 0 X

2 0 0 1 0 X 1 X X 1

3 0 1 0 0 X X 0 1 X 0 1 1 X

4 0 1 1 1 X X 1 X 1 1 0 X 1

5 1 0 0 X 1 0 X

1 1 X 0

1 0 0 0

Design of synchronous counters

state Q2 Q1 Q0 J2 K2 J1 K1 J0 K0

CLK Qn Qn+1 J K

1 0 0 0 0 X 0 X 1 X

0 0 0 X

2 0 0 1 0 X 1 X X 1

3 0 1 0 0 X X 0 1 X 0 1 1 X

4 0 1 1 1 X X 1 X 1 1 0 X 1

5 1 0 0 X 1 0 X 0 X

1 1 X 0

1 0 0 0

Design of synchronous counters

state Q2 Q1 Q0 J2 K2 J1 K1 J0 K0

CLK Qn Qn+1 J K

1 0 0 0 0 X 0 X 1 X

0 0 0 X

2 0 0 1 0 X 1 X X 1

3 0 1 0 0 X X 0 1 X 0 1 1 X

4 0 1 1 1 X X 1 X 1 1 0 X 1

5 1 0 0 X 1 0 X 0 X

1 1 X 0

1 0 0 0

*** We now have the truth tables for J0 , K0 , J1 , K1 , J2 , K2 in terms of Q0 , Q1 , Q2 .
**

The next step is to find logical functions for each of them.

Design of synchronous counters

state Q2 Q1 Q0 J2 K2 J1 K1 J0 K0

CLK Qn Qn+1 J K

1 0 0 0 0 X 0 X 1 X

0 0 0 X

2 0 0 1 0 X 1 X X 1

3 0 1 0 0 X X 0 1 X 0 1 1 X

4 0 1 1 1 X X 1 X 1 1 0 X 1

5 1 0 0 X 1 0 X 0 X

1 1 X 0

1 0 0 0

*** We now have the truth tables for J0 , K0 , J1 , K1 , J2 , K2 in terms of Q0 , Q1 , Q2 .
**

The next step is to find logical functions for each of them.

* Note that we have not tabulated the J and K values for those combinations of

Q0 , Q1 , Q2 which do not occur in the state transition table (such as

Q2 Q1 Q0 = 110). We treat these as don’t care conditions (next slide).

**M. B. Patil, IIT Bombay
**

Design of synchronous counters

Q2 Q1 Q2 Q1

Q0 00 01 11 10 Q0 00 01 11 10

0 0 0 X X 0 X X X 1

J2 K2

1 0 1 X X 1 X X X X

state Q2 Q1 Q0 J2 K2 J1 K1 J0 K0

1 0 0 0 0 X 0 X 1 X Q2 Q1 Q2 Q1

2 0 0 1 0 X 1 X X 1 Q0 00 01 11 10 Q0 00 01 11 10

3 0 1 0 0 X X 0 1 X 0 0 X X 0 0 X 0 X X

J1 K1

4 0 1 1 1 X X 1 X 1 1 1 X X X 1 X 1 X X

5 1 0 0 X 1 0 X 0 X

1 0 0 0 Q2 Q1 Q2 Q1

Q0 00 01 11 10 Q0 00 01 11 10

0 1 1 X 0 0 X X X X

J0 K0

1 X X X X 1 1 1 X X

**M. B. Patil, IIT Bombay
**

Design of synchronous counters

Q2 Q1 Q2 Q1

Q0 00 01 11 10 Q0 00 01 11 10

0 0 0 X X 0 X X X 1

J2 K2

1 0 1 X X 1 X X X X

state Q2 Q1 Q0 J2 K2 J1 K1 J0 K0

1 0 0 0 0 X 0 X 1 X Q2 Q1 Q2 Q1

2 0 0 1 0 X 1 X X 1 Q0 00 01 11 10 Q0 00 01 11 10

3 0 1 0 0 X X 0 1 X 0 0 X X 0 0 X 0 X X

J1 K1

4 0 1 1 1 X X 1 X 1 1 1 X X X 1 X 1 X X

5 1 0 0 X 1 0 X 0 X

1 0 0 0 Q2 Q1 Q2 Q1

Q0 00 01 11 10 Q0 00 01 11 10

0 1 1 X 0 0 X X X X

J0 K0

1 X X X X 1 1 1 X X

*** We treat the unused states (Q2 Q1 Q0 = 101, 110, 111) as (additional) don’t care conditions.
**

Since these are different from the don’t care conditions arising from the state transition

table, we mark them with a different colour.

**M. B. Patil, IIT Bombay
**

Design of synchronous counters

Q2 Q1 Q2 Q1

Q0 00 01 11 10 Q0 00 01 11 10

0 0 0 X X 0 X X X 1

J2 K2

1 0 1 X X 1 X X X X

state Q2 Q1 Q0 J2 K2 J1 K1 J0 K0

1 0 0 0 0 X 0 X 1 X Q2 Q1 Q2 Q1

2 0 0 1 0 X 1 X X 1 Q0 00 01 11 10 Q0 00 01 11 10

3 0 1 0 0 X X 0 1 X 0 0 X X 0 0 X 0 X X

J1 K1

4 0 1 1 1 X X 1 X 1 1 1 X X X 1 X 1 X X

5 1 0 0 X 1 0 X 0 X

1 0 0 0 Q2 Q1 Q2 Q1

Q0 00 01 11 10 Q0 00 01 11 10

0 1 1 X 0 0 X X X X

J0 K0

1 X X X X 1 1 1 X X

*** We treat the unused states (Q2 Q1 Q0 = 101, 110, 111) as (additional) don’t care conditions.
**

Since these are different from the don’t care conditions arising from the state transition

table, we mark them with a different colour.

* We will assume that a suitable initialization facility is provided to ensure that the counter

starts up in one of the five allowed states (say, Q2 Q1 Q0 = 000).

**M. B. Patil, IIT Bombay
**

Design of synchronous counters

Q0 00 01 11 10 Q0 00 01 11 10

0 0 0 X X 0 X X X 1

J2 K2

1 0 1 X X 1 X X X X

state Q2 Q1 Q0 J2 K2 J1 K1 J0 K0

1 0 0 0 0 X 0 X 1 X Q2 Q1 Q2 Q1

2 0 0 1 0 X 1 X X 1 Q0 00 01 11 10 Q0 00 01 11 10

3 0 1 0 0 X X 0 1 X 0 0 X X 0 0 X 0 X X

J1 K1

4 0 1 1 1 X X 1 X 1 1 1 X X X 1 X 1 X X

5 1 0 0 X 1 0 X 0 X

1 0 0 0 Q2 Q1 Q2 Q1

Q0 00 01 11 10 Q0 00 01 11 10

0 1 1 X 0 0 X X X X

J0 K0

1 X X X X 1 1 1 X X

*** We treat the unused states (Q2 Q1 Q0 = 101, 110, 111) as (additional) don’t care conditions.
**

Since these are different from the don’t care conditions arising from the state transition

table, we mark them with a different colour.

* We will assume that a suitable initialization facility is provided to ensure that the counter

starts up in one of the five allowed states (say, Q2 Q1 Q0 = 000).

* From the K-maps, J2 = Q1 Q0 , K2 = 1, J1 = Q0 , K1 = Q0 , J0 = Q2 , K0 = 1.

**M. B. Patil, IIT Bombay
**

Design of synchronous counters: verification

J2 Q2 J1 Q1 J0 Q0

J Q J Q J Q

K Q K Q K Q

K2 K1 K0

CLK

1

CLK

Q0

Q1

Q2

0.04 0.14 0.24 0.34

time (msec)

(SEQUEL file: ee101_counter_6.sqproj)

**M. B. Patil, IIT Bombay
**

Design of synchronous counters: verification

J2 Q2 J1 Q1 J0 Q0

J Q J Q J Q

K Q K Q K Q

K2 K1 K0

CLK

1

CLK

Q0

Q1

Q2

0.04 0.14 0.24 0.34

time (msec)

(SEQUEL file: ee101_counter_6.sqproj)

* J2 = Q1 Q0 , K2 = 1, J1 = Q0 , K1 = Q0 , J0 = Q2 , K0 = 1.

**M. B. Patil, IIT Bombay
**

Design of synchronous counters: verification

J2 Q2 J1 Q1 J0 Q0

J Q J Q J Q

K Q K Q K Q

K2 K1 K0

CLK

1

CLK

Q0

Q1

Q2

0.04 0.14 0.24 0.34

time (msec)

(SEQUEL file: ee101_counter_6.sqproj)

* J2 = Q1 Q0 , K2 = 1, J1 = Q0 , K1 = Q0 , J0 = Q2 , K0 = 1.

* Note that the design is independent of whether positive or negative edge-triggered flip-flops

are used.

M. B. Patil, IIT Bombay

Combination of counters

Counter 1

Clock 1

mod-k1

Counter 2

Clock 2

mod-k2

*** Consider two counters, Counter 1 (mod-k1 ) and Counter 2 (mod-k2 ).
**

(Each of them can be ripple or synchronous type.)

Combination of counters

Counter 1

Clock 1

mod-k1

Counter 2

Clock 2

mod-k2

*** Consider two counters, Counter 1 (mod-k1 ) and Counter 2 (mod-k2 ).
**

(Each of them can be ripple or synchronous type.)

* Since Counter 1 has k1 states and Counter 2 has k2 states, we can get a new counter with

k1 k2 states if appropriate synchronisation is provided between the two clocks.

Combination of counters

Counter 1

Clock 1

mod-k1

Counter 2

Clock 2

mod-k2

*** Consider two counters, Counter 1 (mod-k1 ) and Counter 2 (mod-k2 ).
**

(Each of them can be ripple or synchronous type.)

* Since Counter 1 has k1 states and Counter 2 has k2 states, we can get a new counter with

k1 k2 states if appropriate synchronisation is provided between the two clocks.

* There are two ways of providing synchronisation:

Combination of counters

Counter 1

Clock 1

mod-k1

Counter 2

Clock 2

mod-k2

*** Consider two counters, Counter 1 (mod-k1 ) and Counter 2 (mod-k2 ).
**

(Each of them can be ripple or synchronous type.)

* Since Counter 1 has k1 states and Counter 2 has k2 states, we can get a new counter with

k1 k2 states if appropriate synchronisation is provided between the two clocks.

* There are two ways of providing synchronisation:

- derive Clock 2 from Clock 1 (using some decoding logic, if necessary)

Combination of counters

**Counter 1 Decoding Counter 2
**

Clock 1

Clock 1

Counter 1 mod-k1 logic Clock 2 mod-k2

mod-k1

Counter 2

Clock 2

mod-k2

*** Consider two counters, Counter 1 (mod-k1 ) and Counter 2 (mod-k2 ).
**

(Each of them can be ripple or synchronous type.)

* Since Counter 1 has k1 states and Counter 2 has k2 states, we can get a new counter with

k1 k2 states if appropriate synchronisation is provided between the two clocks.

* There are two ways of providing synchronisation:

- derive Clock 2 from Clock 1 (using some decoding logic, if necessary)

Combination of counters

**Counter 1 Decoding Counter 2
**

Clock 1

Clock 1

Counter 1 mod-k1 logic Clock 2 mod-k2

mod-k1

Counter 2

Clock 2

mod-k2

*** Consider two counters, Counter 1 (mod-k1 ) and Counter 2 (mod-k2 ).
**

(Each of them can be ripple or synchronous type.)

* Since Counter 1 has k1 states and Counter 2 has k2 states, we can get a new counter with

k1 k2 states if appropriate synchronisation is provided between the two clocks.

* There are two ways of providing synchronisation:

- derive Clock 2 from Clock 1 (using some decoding logic, if necessary)

- drive the two counters with the same clock

Combination of counters

**Counter 1 Decoding Counter 2
**

Clock 1

Clock 1

Counter 1 mod-k1 logic Clock 2 mod-k2

mod-k1

**Counter 2 Counter 1 Counter 2
**

Clock 2 mod-k1 mod-k2

mod-k2

common

clock

*** Consider two counters, Counter 1 (mod-k1 ) and Counter 2 (mod-k2 ).
**

(Each of them can be ripple or synchronous type.)

* Since Counter 1 has k1 states and Counter 2 has k2 states, we can get a new counter with

k1 k2 states if appropriate synchronisation is provided between the two clocks.

* There are two ways of providing synchronisation:

- derive Clock 2 from Clock 1 (using some decoding logic, if necessary)

- drive the two counters with the same clock

M. B. Patil, IIT Bombay

Combination of counters

J0 Q0 J2 Q2 J1 Q1 J0 Q0

J Q J Q J Q J Q

CLK

1 K Q K Q K Q K Q

K0 K2 K1 K0

CLK

1

CLK CLK

t t

Q0 Q0

t t

Q1

t

Q2

t

mod−2 counter mod−5 counter

**M. B. Patil, IIT Bombay
**

Combination of counters

J0 Q0 J2 Q2 J1 Q1 J0 Q0

J Q J Q J Q J Q

CLK

1 K Q K Q K Q K Q

K0 K2 K1 K0

CLK

1

CLK CLK

t t

Q0 Q0

t t

Q1

t

Q2

t

mod−2 counter mod−5 counter

* Let us combine the mod-2 and mod-5 counters to make a mod-10 counter.

**M. B. Patil, IIT Bombay
**

Combination of counters

J0 Q0 J2 Q2 J1 Q1 J0 Q0

J Q J Q J Q J Q

CLK

1 K Q K Q K Q K Q

K0 K2 K1 K0

CLK

1

CLK CLK

t t

Q0 Q0

t t

Q1

t

Q2

t

mod−2 counter mod−5 counter

*** Let us combine the mod-2 and mod-5 counters to make a mod-10 counter.
**

* We will follow two approaches (as described earlier):

A: The clock for the second (mod-5) counter is derived from the first (mod-2) counter.

B: A common clock is used to drive the mod-2 and mod-5 counters.

M. B. Patil, IIT Bombay

Approach A

J0 QA J2 Q2 J1 Q1 J0 Q0

J Q J Q J Q J Q

CLK

1 K Q K Q K Q K Q

K0 K2 K1 K0

1

(SEQUEL file: ee101_counter_7.sqproj)

CLK

QA

Q0

Q1

Q2

1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 8 9 10 1 2 3 4

0.04 0.24 0.44 0.64 0.84 1.04

time (msec)

M. B. Patil, IIT Bombay

Approach B

J0 QA J2 Q2 J1 Q1 J0 Q0

J Q J Q J Q J Q

1 K Q K Q K Q K Q

K0 K2 K1 K0

CLK

1

(SEQUEL file: ee101_counter_8.sqproj)

CLK

QA

Q0

Q1

Q2

1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 8 9 10 1 2 3 4

0.04 0.24 0.44 0.64 0.84 1.04

time (msec)

M. B. Patil, IIT Bombay

Combination of counters

*** Show that, by connecting the Q output of the mod-2 counter (instead of the Q
**

output) to the clock input of the mod-5 counter in the ripple connection

(“Approach A”) circuit, we get a decade counter, counting up from 0000 to

1001.

**M. B. Patil, IIT Bombay
**

Combination of counters

*** Show that, by connecting the Q output of the mod-2 counter (instead of the Q
**

output) to the clock input of the mod-5 counter in the ripple connection

(“Approach A”) circuit, we get a decade counter, counting up from 0000 to

1001.

* Derive appropriate decoding logic for each of the ten counters states (i.e., the

output should be 1 for only that particular state and 0 otherwise).

**M. B. Patil, IIT Bombay
**

Combination of counters

*** Show that, by connecting the Q output of the mod-2 counter (instead of the Q
**

output) to the clock input of the mod-5 counter in the ripple connection

(“Approach A”) circuit, we get a decade counter, counting up from 0000 to

1001.

* Derive appropriate decoding logic for each of the ten counters states (i.e., the

output should be 1 for only that particular state and 0 otherwise).

* Derive appropriate decoding logic which will give a symmetrical square wave (i.e.,

a duty cycle of 50 %) with a frequency of fc /10, where fc is the clock frequency.

**M. B. Patil, IIT Bombay
**

Combination of counters

*** Show that, by connecting the Q output of the mod-2 counter (instead of the Q
**

output) to the clock input of the mod-5 counter in the ripple connection

(“Approach A”) circuit, we get a decade counter, counting up from 0000 to

1001.

* Derive appropriate decoding logic for each of the ten counters states (i.e., the

output should be 1 for only that particular state and 0 otherwise).

* Derive appropriate decoding logic which will give a symmetrical square wave (i.e.,

a duty cycle of 50 %) with a frequency of fc /10, where fc is the clock frequency.

* Verify your design by simulation.

M. B. Patil, IIT Bombay

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